Main Power Input Protection and Distribution¶
This section documents the protection and control circuitry for the primary power entry path of the system.
This path covers:
Battery / alternator input → protection stage → MOSFET isolation → downstream regulators (LMR3651) → system 5 V and 3.3 V rails.
It protects the entire board power system, including:
• alternator field drive power path
• LMR3651 regulator input
• 5 V system rail
• 3.3 V rail (derived downstream)
It does NOT protect external sensor inputs. Sensor input protection is implemented separately and documented in another section.
Device Overview¶
Part: TPS48000‑Q1
Package: DGX (VSSOP‑19)
Function:
100 V automotive high‑side driver with protection.
Key features used in this design:
• Reverse polarity tolerance to −65 V
• Programmable overvoltage protection
• Programmable short‑circuit protection
• Fast MOSFET shutdown (~5 µs)
• Integrated charge pump for N‑MOSFET control
Although the device is AEC‑Q100 automotive qualified, it is used here in a marine electrical system. Automotive electrical environments are generally harsher than typical marine systems (load dump, cold crank, large transients), making the device suitable for marine use.
EN/UVLO (Pin 1) – Enable / Undervoltage Lockout¶
Thresholds from datasheet:
| Parameter | Value |
|---|---|
| Rising | 1.176–1.287 V |
| Typical | 1.23 V |
| Falling | 1.09–1.184 V |
| Typical | 1.136 V |
Divider network:
R1 = 750 kΩ
R2 = 249 kΩ
Tolerance = 0.1 %
Total resistance:
999 kΩ
Battery turn‑on voltage:
Vbat = Vth × (R1 + R2) / R2
Typical:
1.23 V × (999 kΩ / 249 kΩ)
≈ 4.94 V
Turn‑on voltage range:
| Condition | Battery Voltage |
|---|---|
| Minimum | 4.72 V |
| Typical | 4.94 V |
| Maximum | 5.17 V |
Turn‑off voltage:
Typical ≈ 4.57 V
Purpose:
This divider ensures the controller does not attempt to operate when the input supply is extremely low and guarantees clean startup behavior.
Divider current:
| VIN | Current |
|---|---|
| 12 V | 12 µA |
Overvoltage Protection (OVP)¶
The OV pin detects excessive battery voltage.
Divider network:
R_top = 511 kΩ (0.1 %)
R_bottom = 10.2 kΩ (0.1 %)
Total resistance:
521.2 kΩ
Divider ratio:
Vov = Vin × (10.2k / 521.2k)
≈ 0.01957
OV comparator thresholds:
| Parameter | Voltage |
|---|---|
| Rising | 1.171–1.278 V |
| Typical | 1.225 V |
| Falling | 1.088–1.186 V |
| Typical | 1.138 V |
Resulting battery trip levels:
| Condition | Voltage |
|---|---|
| Minimum trip | 59.8 V |
| Typical trip | 62.6 V |
| Maximum trip | 65.3 V |
Recovery levels:
| Condition | Voltage |
|---|---|
| Earliest re‑enable | 55.6 V |
| Typical re‑enable | 58.2 V |
| Latest re‑enable | 60.6 V |
Divider current:
| VIN | Current |
|---|---|
| 12 V | 23 µA |
| 60 V | 115 µA |
Behavior:
When OV exceeds the rising threshold, the controller pulls PD to SRC, discharging the MOSFET gates and shutting off the pass FETs.
Shutdown propagation delay:
≈ 4.5 µs typical
≈ 5.4 µs max
Short‑Circuit Protection (SCP)¶
Current sensing is performed across a 2 mΩ shunt resistor.
Part used:
HoLLR2010‑1.5W‑2mR‑1%
Important layout requirement:
Because the sense voltage is only ~30 mV at trip, the resistor must be Kelvin sensed with dedicated sense traces to the CS+ and CS− pins. PCB trace resistance can otherwise introduce significant error.
Trip calculation:
RISCP = (I × Rsense − 19 mV) / 2 µA
For 15 A target:
≈ 5.5 kΩ
Selected resistor:
5.6 kΩ
Result:
Trip current ≈ 15.1 A
Sense voltage:
≈ 30.2 mV
Fault Timer¶
Timer capacitor:
CTMR = 1 µF
Trip delay:
t = (C × 1.1 V) / 80 µA
≈ 13.8 ms
Retry interval:
t = 22.7×10⁶ × C
≈ 22.7 s
Timer behavior:
CTMR charges at 80 µA during overcurrent and discharges at 2.5 µA when the fault clears.
Because charge is much faster than discharge (~32:1 ratio), repeated PWM current peaks accumulate toward a trip event.
This configuration acts as a sustained fault detector, not a cycle‑by‑cycle current limiter.
PWM Interaction¶
PWM frequency ≈ 1200 Hz
PWM period:
≈ 833 µs
Since the SCP delay is 13.8 ms, many PWM cycles occur before a trip decision is made.
Therefore the protection responds to sustained overcurrent, not short PWM spikes.
Note, all of this analysis assumes a squarewave current profile, but in reality it will be smoother. Changing the switching frequency will not meaningfully affect the behavior, just shift the response timeframe slighly.
Transient Protection¶
A SMBJ64CA bidirectional TVS diode is placed across VIN and ground.
Key parameters:
| Parameter | Value |
|---|---|
| Stand‑off voltage | 64 V |
| Breakdown voltage | 71.1–78.6 V |
| Clamp voltage | 103 V @ 5.8 A |
| Peak pulse power | 600 W (10/1000 µs) |
The TVS remains off during normal operation.
It begins conducting only once voltage exceeds roughly 71 V.
Downstream Energy Buffer¶
Capacitance between the MOSFET stage and regulator input:
| Capacitor | Quantity |
|---|---|
| 4.7 µF | ×4 |
| 100 nF | ×1 |
| 2.2 µF | ×1 |
| 220 nF | ×1 |
Total ≈ 21 µF
This slows voltage rise during transient events.
Example:
If 20 A surge current enters the node:
dV/dt = I / C
≈ 0.95 V/µs
With a ~5 µs shutdown delay, voltage rises roughly 5 V before isolation occurs.
Reverse Polarity Protection¶
Protection is provided by back‑to‑back N‑MOSFETs controlled by the TPS48000.
This arrangement cancels the MOSFET body diodes and blocks current when the battery is connected backwards.
The TPS48000 itself tolerates reverse input voltage to −65 V.
A Schottky diode from GND to VOUT clamps negative excursions at the protected rail.
Lightning‑Induced Transients¶
Nearby lightning strikes can couple large voltage spikes into vessel wiring.
These surges may be positive or negative relative to ground.
Protection layers:
- TVS diode clamps large spikes
- Input capacitors absorb high‑frequency energy
- TPS48000 detects overvoltage
- MOSFETs isolate downstream electronics
The system is not designed to survive a direct lightning strike (obviously), but is intended to tolerate induced surges conducted through long marine wiring as best possible without turning the project into a rabbit hole.
Power Consumption¶
Worst‑case TPS48000 quiescent current used: 55 µA
Battery Present¶
| VIN | EN/UVLO Current | OV Current | TPS48000 IQ | Total |
|---|---|---|---|---|
| 13 V | 13 µA | 25 µA | 55 µA | 93 µA |
| 26 V | 26 µA | 50 µA | 55 µA | 131 µA |
| 52 V | 52 µA | 100 µA | 55 µA | 207 µA |
Total standby dissipation at 52 V:
≈ 10.8 mW
Battery Absent (USB Power)¶
If the battery is physically absent, the TPS48000 front‑end receives no supply and therefore draws zero current from the battery rail.
The TPS2116 power multiplexer then routes USB power to the 5 V system rail.
TPS2116 standby current is only a few microamps and is negligible.
Design Intent¶
This protection system is designed to tolerate:
• alternator load‑dump transients
• long cable inductive spikes
• lightning‑induced surges conducted through vessel wiring
Protection strategy:
- TVS clamps the fastest surge energy
- Input capacitors absorb high‑frequency spikes
- TPS48000 detects faults
- MOSFETs disconnect the load
- Downstream capacitance limits dv/dt
This layered architecture allows reliable operation in harsh marine environments while protecting the regulator.